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PD - 94296A SMPS MOSFET Applications High frequency DC-DC converters IRFR12N25D IRFU12N25D HEXFET(R) Power MOSFET l VDSS 250V RDS(on) max 0.26 ID 14A Benefits l Low Gate-to-Drain Charge to Reduce Switching Losses l Fully Characterized Capacitance Including Effective COSS to Simplify Design, (See App. Note AN1001) l Fully Characterized Avalanche Voltage and Current D-Pak IRFR12N25D I-Pak IRFU12N25D Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 14 9.7 56 144 0.96 30 9.3 -55 to + 175 300 (1.6mm from case ) Units A W W/C V V/ns C Thermal Resistance Parameter RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount)* Junction-to-Ambient Typ. --- --- --- Max. 1.04 50 110 Units C/W Notes through are on page 10 www.irf.com 1 09/21/01 IRFR12N25D/IRFU12N25D Static @ TJ = 25C (unless otherwise specified) Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage V(BR)DSS IDSS IGSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 250 --- --- 3.0 --- --- --- --- Typ. --- 0.29 --- --- --- --- --- --- Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 0.26 VGS = 10V, ID = 8.4A 5.0 V VDS = VGS, ID = 250A 25 VDS = 200V, VGS = 0V A 250 VDS = 160V, VGS = 0V, TJ = 150C 100 VGS = 30V nA -100 VGS = -30V Dynamic @ TJ = 25C (unless otherwise specified) gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 6.8 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- 23 5.8 12 9.1 25 16 9.2 810 130 22 1100 50 130 Max. Units Conditions --- S VDS = 25V, ID = 8.4A 35 I D = 8.4A 8.7 nC VDS = 200V 19 VGS = 10V, --- VDD = 125V --- ID = 8.4A ns --- RG = 6.8 --- VGS = 10V --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 200V, = 1.0MHz --- VGS = 0V, VDS = 0V to 200V Avalanche Characteristics Parameter EAS IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Typ. --- --- --- Max. 250 8.4 14 Units mJ A mJ Diode Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 14 --- --- showing the A G integral reverse --- --- 56 S p-n junction diode. --- --- 1.5 V TJ = 25C, IS = 8.4A, VGS = 0V --- 140 --- ns TJ = 25C, IF = 8.4A --- 710 --- nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRFR12N25D/IRFU12N25D 100 VGS 15V 12V 10V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V TOP 100 VGS 15V 12V 10V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V TOP ID, Drain-to-Source Current (A) ID , Drain-to-Source Current (A) 10 10 1 0.1 5.0V 1 5.0V 0.01 20s PULSE WIDTH Tj = 25C 0.001 0.1 1 10 100 20s PULSE WIDTH Tj = 175C 0.1 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100.00 3.5 I D = 14A ID , Drain-to-Source Current ( ) T J = 175C 10.00 RDS(on) , Drain-to-Source On Resistance 3.0 2.5 (Normalized) 2.0 1.00 T J = 25C 0.10 1.5 1.0 0.01 5.0 7.0 9.0 VDS = 15V 20s PULSE WIDTH 11.0 13.0 15.0 0.5 0.0 -60 -40 -20 0 20 40 60 80 V GS = 10V 100 120 140 160 180 VGS, Gate-to-Source Voltage (V) TJ , Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRFR12N25D/IRFU12N25D 10000 12 VGS = 0V, f = 1 MHZ Ciss = C + Cgd , C gs ds SHORTED Crss = C gd Coss = C + Cgd ds ID = 8.4A 10 VDS = 200V VDS = 125V VDS = 50V C, Capacitance(pF) Ciss VGS, Gate-to-Source Voltage (V) 1000 7 5 100 Coss 2 Crss 10 1 10 100 1000 0 0 5 10 15 20 25 VDS , Drain-to-Source Voltage (V) Q G, Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100.00 T J = 175C 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) 10.00 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 10 100sec 1.00 T J = 25C 1 Tc = 25C Tj = 175C Single Pulse 0.1 1 10 100 1msec VGS = 0V 0.10 0.0 1.0 2.0 3.0 VSD , Source-toDrain Voltage (V) 10msec 1000 VDS , Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRFR12N25D/IRFU12N25D 15 VDS VGS RD 12 D.U.T. + RG -VDD I D , Drain Current (A) 9 VGS Pulse Width 1 s Duty Factor 0.1 % 6 Fig 10a. Switching Time Test Circuit 3 VDS 90% 0 25 50 75 100 125 150 175 TC , Case Temperature ( C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 (Z thJC) 1 D = 0.50 Thermal Response 0.20 0.10 0.1 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) 0.0001 0.001 0.01 0.01 0.00001 Notes: 1. Duty factor D = 2. Peak T J P DM t1 t2 +TC t1/ t 2 = P DM x Z thJC 0.1 1 t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFR12N25D/IRFU12N25D 1 5V 550 VDS L D R IV E R 440 ID TOP 3.4A 5.9A 8.4A BOTTOM RG 20V tp D .U .T IA S + V - DD EAS , Single Pulse Avalanche Energy (mJ) 330 A 0 .0 1 220 Fig 12a. Unclamped Inductive Test Circuit 110 V (B R )D SS tp 0 25 50 75 100 125 150 175 Starting T , Junction Temperature J ( C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. QG 12V .2F 50K .3F QGS VG QGD D.U.T. VGS 3mA + V - DS Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRFR12N25D/IRFU12N25D Peak Diode Recovery dv/dt Test Circuit D.U.T + + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) Power MOSFETs www.irf.com 7 IRFR12N25D/IRFU12N25D D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 6 .7 3 (.2 6 5 ) 6 .3 5 (.2 5 0 ) -A5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 1 .2 7 (.0 5 0 ) 0 .8 8 (.0 3 5 ) 2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 ) 1 .1 4 (.0 4 5 ) 0 .8 9 (.0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) 6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 6 .2 2 (.2 4 5 ) 5 .9 7 (.2 3 5 ) 1.0 2 (.0 4 0 ) 1.6 4 (.0 2 5 ) 1 2 3 0 .5 1 (.0 2 0 ) M IN . 1 0 .4 2 (.4 1 0 ) 9 .4 0 (.3 7 0 ) L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - S OU R CE 4 - D R A IN -B 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 3X 2X 1 .1 4 (.0 4 5 ) 0 .7 6 (.0 3 0 ) 2 .2 8 ( .0 9 0 ) 4 .5 7 ( .1 8 0 ) 0 .8 9 (.0 3 5 ) 0 .6 4 (.0 2 5 ) 0 .2 5 ( .0 1 0 ) M AMB N O TE S : 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) 1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0 .1 6 (.0 0 6 ) . D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WIT H ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN T HE ASSEMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO IRFU120 12 916A 34 ASSEMBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A 8 www.irf.com IRFR12N25D/IRFU12N25D I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6 .7 3 (.26 5 ) 6 .3 5 (.25 0 ) -A 5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 1 .2 7 ( .0 5 0 ) 0 .8 8 ( .0 3 5 ) 2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - SOURCE 4 - D R A IN 6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 1 -B 2.2 8 (.0 9 0) 1.9 1 (.0 7 5) 9 .6 5 ( .3 8 0 ) 8 .8 9 ( .3 5 0 ) 2 3 6 .2 2 ( .2 4 5 ) 5 .9 7 ( .2 3 5 ) N O TE S : 1 D IM E N S IO N IN G & TO L E R A N C IN G P E R A N S I Y 1 4 .5M , 19 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R MS TO J E D E C O U T L IN E TO -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0.1 6 (.0 0 6 ). 3X 1 .1 4 (.0 45 ) 0 .7 6 (.0 30 ) 3X 0 .8 9 (.0 35 ) 0 .6 4 (.0 25 ) M AMB 1 .1 4 ( .0 4 5 ) 0 .8 9 ( .0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) 2 .28 (.0 9 0 ) 2X 0 .2 5 (.0 1 0 ) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN T HE AS SEMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO IRFU120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A ASSEMBLY LOT CODE www.irf.com 9 IRFR12N25D/IRFU12N25D D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16 .3 ( .641 ) 15 .7 ( .619 ) 12.1 ( .47 6 ) 11.9 ( .46 9 ) F E E D D IR E C T IO N 8.1 ( .318 ) 7.9 ( .312 ) FE E D D IR E C T IO N N O T ES : 1 . C O N T R O LLIN G D IME N S IO N : M ILL IM ET E R . 2 . A LL D IM EN S IO N S A R E SH O W N IN M ILLIM ET E R S ( IN C H E S ). 3 . O U TL IN E C O N FO R MS T O E IA -481 & E IA -54 1. 1 3 IN C H 16 m m N O TE S : 1. O U TL IN E C O N F O R M S T O E IA -481 . Notes: Repetitive rating; pulse width limited by max. junction temperature. Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS Starting TJ = 25C, L = 7.1mH RG = 25, IAS = 8.4A. ISD 8.4A, di/dt 150A/s, VDD V(BR)DSS, TJ 175C * When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.09/01 10 www.irf.com |
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